1. Field of the Invention
The present invention relates to a bonding pad structure for a semiconductor circuit and a method of forming the same, and more particularly, to a bonding pad structure that resists electrostatic discharge (ESD) damage and a method of forming the same.
2. Description of the Related Art
Bonding pads are the interfaces between the integrated circuits contained in semiconductor chips and the chip package. A large number of bonding pads are required to transmit power/ground and input/output signals to the chip devices. It is thus important that the bonding pad yield be sufficiently high to ensure a higher yield.
The general bonding pad structure consists of metal layers emanating from the terminals of the chip devices and separated by IMD (intermetal dielectric) layers that typically comprise silicon oxide. An IMD layer separates the uppermost metal layer from a bonding pad pattern formed on the IMD layer. Metal plugs pass through the IMD layers connecting the metal layers to the metal bonding pattern. Wires are bonded to the metal bonding pattern and to the chip package forming electrical connections between the chip and the package. A passivation layer covers the surface, except over bonding sites, sealing the chip to protect it from contaminants and scratches.
A bonding pad structure having slotted metal layers has recently been disclosed in U.S. Pat. No. 5,736,791, for example. FIG. 1 schematically shows the conventional bonding pad structure. The conventional pad structure containing a bonding metal layer 11 and a multiplicity of first metal layers 12 and second metal layers 13, wherein IMD levels 15 separate metal layers 11, 12 and 13. Metal plugs 16 pass through the IMD levels 15 connecting the metal layers 12 and 13 to the bonding metal layer 11. FIG. 2A shows a layout pattern (a top plan view) of the first metal layer 12. The first metal layer 12 has a first wiring layer 22 with a stripe layout, wherein elongated rectangular first slot portions 24 are formed through the first wiring layer 22. FIG. 2B shows a layout pattern (a top plan view) of the second metal layer 13. The second metal layer 13 has a second wiring layer 23 with a stripe layout, wherein elongated rectangular second slot portions 25 are formed through the second wiring layer 23. It is noted that the direction of the first wiring layer 22 is perpendicular to that of the second wiring layer 23. Also, the metal plugs 16 are located at the intersecting points of the first and second wiring layers 22 and 23.
The conventional bonding pad structure can prevent the dielectric layer from cracking, but does not address potential electrostatic discharge (ESD) damage. ESD can occur when electrostatic charge accumulates. This can occur whenever semiconductor devices are handled or for various other reasons. Input/output pads (also referred to as bonding pads) are particularly vulnerable to ESD. ESD can potentially result in the destruction of the conventional pad structure when the high ESD current (e.g. >2 amp.) flows into the edge portion of the conventional pad structure, thereby seriously degrading the device performance.
FIG. 3 depicts an ESD event occurring at the edge portion of the conventional pad structure. For example, an ESD protection device 30 is connected to one side of the first metal layer 12. When the ESD current, represented by arrows 32, flows into the edge portion 34 of the first metal layer 12 of the conventional pad structure, the edge portion 34 is easily damaged by ESD.
In U.S. Pat. No. 5,736,791, Noriaki et al disclose a bonding pad structure utilizing via holes and slots formed in metal layers. This pad structure is generally referred to as a slotted pad structure. The slots of the pad structure are resistant to cracks caused during wire bonding. Though effective, this structure cannot sustain high ESD current.
In U.S. Pat. No. 5,739,587, Sato et al disclose a bonding pad structure containing via holes or grooves which prevent moisture from entering device areas. This bonding pad structure does not utilize slots formed in metal layers. Additionally, this structure does not teach how to sustain high ESD current during an ESD event.
In U.S. Pat. No. 6,028,367, Chen discloses a bonding pad structure for improving heat conductance. This structure includes a bonding pad substantially surrounded and insulated by an IMD layer and formed of two metal layers and metal via plugs connected therebetween, and a heat dissipating ring surrounding and spaced-apart from the bonding pad. This bonding pad structure does not utilize slots. Moreover, this structure does not teach how to sustain high ESD current during an ESD event.
In U.S. Patent application publication No. 2002/0135032, Kwon discloses a semiconductor device for ESD protection. This device includes a plurality of transistors having a multi-fingered structure, a plurality of multilayer interconnections separated from one another formed in proportion to the number of common drain regions of the transistors and connected to the common drain regions of each transistor, a pad conductive layer formed on the multilayer interconnections, and a plurality of contact plugs for connecting multilayer interconnections to one another and for connecting the multilayer interconnections to the pad conductive layer so that a current flowing through the common drain regions of the transistors only passes through the multilayer interconnections connected to the common drain regions and may flow into the pad conductive layer. The bonding pad structure of this semiconductor device, however, utilizes slots formed in each metal layer. Additionally, it does not teach how to sustain high ESD current during an ESD event.